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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-12551-2E
8-bit Proprietary Microcontrollers
CMOS
F2MC-8L MB89051 Series
MB89F051/MB89051
s DESCRIPTION
The MB89051 series is a general-purpose, single-chip microcontroller that features a compact instruction set and contains a range of peripheral function set and timers, serial interface, a PWM timer, the USB hub function and the USB function. The USB hub function, in particular, supports five down ports (one of them is dedicated to an internal function) allowing them to interface with other USB devices. The microcontrollers also contain one USB function channel to support full speed.
s FEATURES
* Package type 64-pin LQFP Package (0.65 mm pitch) * High-speed operations at low voltage Minimum execution time : 0.33 s (Automatically generates a 12 MHz main clock and a 48 MHz USB interface synchronization clock with an externally supplied 6 MHz clock and the internal PLL circuit.) (Continued)
s Package
64-pin plastic LQFP
(FPT-64P-M09)
MB89051 Series
* F2MC-8L CPU core Instruction set that is optimum to the controllers -Multiplication and division instructions -16-bit arithmetic operations -branch instructions by bit testing -bit manipulation instructions, etc. * PLL clock control The internal PLL clock circuit allows the use of low-speed clocks which are advantageous to noise characteristics. (6 MHz externally-supplied clock12 MHz internal system clock) * Various timers 8-bit PWM timer (can be used as either 8-bit PWM timer 2 channels or PPG timer 1 channel) Internal 21-bit timebase timer * Internal USB transceiver circuit (Compatible with full and low speeds) * USB hub USB function Compliant to USB Protocol Revision 1.0 Five downstream port channels (One of these channels is dedicated to a function.) Automatically responds to all USB protocols by hardware. Descriptor configuration is provided as ROM data for automatic responding by hardware (Vender ID and product ID) . String data is not supported. Allows switching between BUS power supply and own power supply mode. Power supply to the USB down port is controlled port by port. * USB function USB function Compliant to USB Protocol Revision 1.0 Support for full speed when using hub Support for both low and full speeds when using function Allows four endpoints to be specified at maximum. Types of transfer supported: control/interrupt/bulk/isochronous Built-in DMAC (Maps the buffer for each endpoint on to the internal RAM to directly access the memory for function's send and receive data.) * UART/SIO, SIO Serial Interface Built-in UART/SIO function (selectable by switching) x 1 channel Built-in SIO (3.3 V) x 2 channels * I2C interface*1 Supports Philips I2C bus standards Uses a two-wire data transfer protocol Master/slave send/receive * External interrupt External interrupt (level detection x 7 channels) Seven inputs are independent of one another and can also be used for resetting from low-power consumption mode (the L-level detection feature available) . * Clock output functions Able for 12 MHz*2 and 6 MHz*2 clocks to output. (dedicated pins, 3 V) * Low power consumption (standby mode supported) Stop mode (There is almost no current consumption since oscillation stops.) Sleep mode (This mode stops the running CPU.) (Continued)
2
MB89051 Series
(Continued) * A maximum of 41 general-purpose I/O ports General-purpose I/O ports (CMOS) : 37 (7 of 3 V ports) General-purpose I/O ports (Nch open drain) : 4 * Power supply Supply voltage: 3.3 V 0.3 V or 5.0 V 0.5 V * Operating temperature TA = -40 to +85 C (When the USB function is not in use.) TA = 0 C to +70 C (When the USB function is in use.)
*1 : I2C license The customer is licensed to use Philips I2C patent when using this product in an I2C system that complies with the Philips I2C standard specifications. *2 : When an external supply clock is at 6 MHz.
3
MB89051 Series
s PRODUCT LINEUP
Part number Parameter ROM size RAM size Package Others MASK product Number of instructions Instruction bit length Instruction length Data bit length Minimum execution time Interrupt processing time : 136 : 8 bits : 1 to 3 bytes : 1, 8, and 16 bits : 0.33 s (6 MHz) : 3 s (6 MHz) MB89051 32 KB 2 KB LQFP-64 (FPT-64P-M09) FLASH product/EVA product MB89F051 32 KB (FLASH)
CPU functions
GeneralGeneral purpose I/O ports (37 : CMOS (7 of 3 V ports ) , 4 : Nch open drain) purpose ports Upstream port : 1 channel Downstream port : 5 channels (One is dedicated to an internal function.) Port power supply control method : By individual port Allows selection between own power supply and bus power supply Supports full speed : when using hub Supports full and low speeds : when using function End point max 4 Built-in DMAC (Can be set to DMA transfer to the internal RAM) 8-bit PWM timer operation 2 channels (can also be used as a PPG 1 channel timer) Allows switching between UART (clock-synchronous/asynchronous data transfer allowed) and SIO (simple serial transfer). SIO (simple serial) x 2 channels (3 V) One channel. Supports Phillips I2C bus standards. Uses a 2-wire protocol for communications with other devices. 21-bit timebase timer Allows clock output of 12 MHz* and 6 MHz* (3 V) Sleep mode and Stop mode
USB hub
Peripheral functions
USB function
PWM timer UART SIO I2C interface Timebase timer Clock output SIO
Standby mode
* : When external supply clock is at 6 MHz.
4
MB89051 Series
s DIFFERENCES AMONG PRODUCTS
1. Memory Size
* Before evaluating using the FLASH product, it is necessary to confirm its differences from the product that will actually be used.
2. Current Consumption
* When operating at low speed, FLASH products will consume more current than mask ROM products. However, in sleep/stop mode the current consumption is the same. * For detailed information on each package, see "sPACKAGE DIMENSIONS"
3. USB Pull-up Resistor control
* Remains in high impedance state until USB connection take place. Before the USB connection, use USBP pin output to control pull-up resistance by software. * The example of connection MB89051 series Host PC
3.3 V 1.5 k D+
USBP pin RPVP pin
D-
RPVM pin
5
MB89051 Series
s PIN ASSIGNMENT
(TOP VIEW)
P33/INT3/SO1 P32/INT2/SI1 P31/INT1 D4VM D4VP D3VM D3VP D2VM D2VP D5VM D5VP USBP RPVM RPVP C VCC P34/INT4/SCK1 P35/INT5/SCK2 P36/INT6/SO2 P37/INT7/SI2 CLK1 CLK2 P40/POW5 P41/POW2 P42/POW3 P43/POW4 P44/UCK P45/UO P46/UI/PWM1 VSS P47/PWM2 MOD2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17
6
P53/SDA P54/SCL RST MOD0 MOD1 X0 X1 VSS P27 P26 P25 P24 P23 P22 P21 P20
(FPT-64P-M09)
MB89051 Series
s PIN DESCRIPTION
Pin No. Pin name P34/INT4/ SCK1 P35/INT5/ SCK2 P36/INT6/ SO2 Circuit type E Function General-purpose CMOS I/O pin The external interrupt input is a hysteresis input. (Level detection) SIO1 clock I/O General-purpose CMOS I/O pin The external interrupt input is a hysteresis input. (Level detection) SIO2 clock I/O General-purpose CMOS I/O pin The external interrupt input is a hysteresis input. (Level detection) SIO2 serial data output General-purpose CMOS I/O pin The external interrupt input is a hysteresis input. (Level detection) SIO2 serial data input 6 MHz clock output pin (When external supply clock is at 6 MHz.) 12 MHz clock output pin (When external supply clock is at 6 MHz.) General-purpose CMOS I/O pin This pin also serves as USB Down Port power control signal. General-purpose CMOS I/O pin This pin also serves as USB Down Port power control signal. General-purpose CMOS I/O pin This pin also serves as USB Down Port power control signal. General-purpose CMOS I/O pin This pin also serves as USB Down Port power control signal. General-purpose CMOS I/O pin UART/S10 clock I/O General-purpose CMOS I/O pin UART/S10 serial data output Nch open drain general-purpose I/O pin UART/S10 serial data input PWM timer Power supply pin (GND) Nch open drain general-purpose I/O pin PWM timer An operating mode designation pin. Connect directly to Vss. Nch open drain general-purpose I/O pin Also serve as I2C interface data input/output pin. Nch open drain general-purpose I/O pin Also serve as I2C interface clock input/output pin. Reset pin (Reset on the negative logic low level.) An operating mode designation pin. Connect directly to Vss. An operating mode designation pin. Connect directly to Vss.
1
2
E
3
B
4 5 6 7 8 9 10 11 12
P37/INT7/SI2 CLK1 CLK2 P40/POW5 P41/POW2 P42/POW3 P43/POW4 P44/UCK P45/UO P46/UI/ PWM1 VSS P47/PWM2 MOD2 P53/SDA P54/SCL RST MOD0 MOD1
E M M B B B B E B
13 14 15 16 17 18 19 20 21
N K F K K I F F
(Continued)
7
MB89051 Series
Pin No. 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Pin name X0 X1 VSS P27 P26 P25 P24 P23 P22 P21 P20 P17 P16 P15 P14 P13 P12 P11 P10 P07 P06 P05 P04 P03 P02 P01 P00 VCC C RPVP RPVM USBP D5VP D5VM
Circuit type A B B B B B B B B B B B B B B B B B B B B B B B B
Function Pins for the connection of crystal oscillation circuit.(6 MHz) Power supply pin (GND) General-purpose CMOS I/O pin* General-purpose CMOS I/O pin* General-purpose CMOS I/O pin* General-purpose CMOS I/O pin* General-purpose CMOS I/O pin* General-purpose CMOS I/O pin* General-purpose CMOS I/O pin* General-purpose CMOS I/O pin* General-purpose CMOS I/O pin General-purpose CMOS I/O pin General-purpose CMOS I/O pin General-purpose CMOS I/O pin General-purpose CMOS I/O pin General-purpose CMOS I/O pin General-purpose CMOS I/O pin General-purpose CMOS I/O pin General-purpose CMOS I/O pin General-purpose CMOS I/O pin General-purpose CMOS I/O pin General-purpose CMOS I/O pin General-purpose CMOS I/O pin General-purpose CMOS I/O pin General-purpose CMOS I/O pin General-purpose CMOS I/O pin Power supply pin. Connect an external capacitor of 0.1 F. When using with 3.3 V power supply, connect this pin with the Vcc pin to set to 3.3 V input.
USBDRV USB route port + pin USBDRV USB router port - pin L USB pull-up resistance connection pin. USBDRV USB down port 5 + pin USBDRV USB down port 5 - pin
* : For output only on the emulator.
(Continued)
8
MB89051 Series
(Continued)
Pin No. 56 57 58 59 60 61 62 Pin name D2VP D2VM D3VP D3VM D4VP D4VM P31/INT1 Circuit type USBDRV USB down port 2 + pin USBDRV USB down port 2 - pin USBDRV USB down port 3 + pin USBDRV USB down port 3 - pin USBDRV USB down port 4 + pin USBDRV USB down port 4 - pin B General-purpose CMOS I/O pin External interrupt input (Hysteresis input (level detection) ) General-purpose CMOS I/O pin External interrupt input (Hysteresis input (level detection) ) SIO1 serial data input General-purpose CMOS I/O pin External interrupt input (Hysteresis input (level detection) ) SIO1 serial data output Function
63
P32/INT2/SI1
E
64
P33/INT3/ SO1
B
9
MB89051 Series
s I/O CIRCUIT TYPE
Type
X1
Circuit
Remarks * Oscillation feedback resistance : 1 M approx.
A
X0
Stanby control signal * CMOS I/O
R Pch Pch
Pullup control register
B
Nch
Stanby control signal
R Pch Pch
Input
* CMOS I/O * Hysteresis input Pullup control register
E
Nch
Stanby control signal
Port input Resource input * CMOS input
F
Input * Hysteresis I/O * Pullup resistance
Pch
R
I
Nch
Input
(Continued)
10
MB89051 Series
(Continued)
Type Circuit * USB I/O D input
D+ D-
+
Remarks
D- input Differential input Full D+ output
USBDRV
Full D- output Low D+ output Low D- output Direction Speed * Nch open drain I/O
Nch
K Stanby control signal
Input
* USB pull-up resistance connection
Pch
L
Nch
* Clock output
Pch
M
Nch
* Nch open drain I/O * Hysteresis input N Stanby control signal
Nch
Port input Resource input 11
MB89051 Series
s HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than Vcc or lower than Vss is applied to input or output pins other than the medium- and high-voltage pins or if voltage higher than the rating is applied between Vcc and Vss. When latchup occurs, power supply current increases rapidly and might thermally damage elements.When using, take great care not to exceed the absolute maximum ratings. Also take care to prevent the analog input from exceeding the digital power supply (Vcc) when the power supply to the analog power system is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions and latchup leading to permanent damage to the pins.These unused pins should be connected to a pullup or pulldown resistance of at least 2 k between the pin and the power supply. Unused I/O pins should be placed in output state to leave it open or pins that are in input state should be handled the same as unused input pins.
3. Note to noise in the External Reset Pin (RST)
If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the external reset pin (RST).
4. Power Supply Voltage Fluctuations
Although Vcc power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that Vcc ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 Hz to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.
5. Note on the clock during operation
This microcontroller uses a PLL for generating the main clock signal. If the oscillator is removed or the clock input stops during operation, therefor, the microcontroller may keep on operating at the free-running frequency of the self-oscillation circuit in the PLL. The operation is not however guaranteed.
6. About port 2 (P20 to P27)
Port 2 serves as an output-only terminal on the emulator.
12
MB89051 Series
s PROGRAMMING AND ERASING FLSH MEMORY
1. Flash Memory
The flash memory is located between 8000H and FFFFH in the CPU memory map and incorporates a flash memory interface circuit that allows read access and program access from the CPU to be performed in the same way as mark ROM. Programming and erasing flash memory is also performed via the flash memory interface circuit by executing instructions in the CPU. This enables the flash memory to be updated in place under the control of the CPU, providing an efficient method of updating program and data.
2. Flash Memory Features
* * * * * * * *
32 Kbyte x 8-bit configuration (16 K + 8 K + 8 K sectors) Automatic programming algorithm (Embedded Algorithm* : Equivalent to MBM29LV200) Includes an erase pause and restart function Data polling and toggle bit for detection of program/erase completion Detection of program/erase completion via CPU interrupt Compatible with JEDEC-standard command Sector Protection (sectors can be combined in any combination) No. of program/erase cycles : 10,000 (Min)
* : Embedded Algorithm is a trademark of Advanced Micro Devices.
3. Procedure for Programming and Erasing Flash Memory
Programming and reading flash memory cannot be performed at the same time. Accordingly, to program or erase flash memory, the program must first be copied from flash memory to RAM so that programming can be performed without program access from flash memory.
4. Flash Memory Register
Address bit7
002EH
* Control status register (FMCS)
bit6 bit5 WE R/W bit4 bit3 bit2 bit1 bit0 Reserved R/W
Initial value
000X00X0B
INTE RDYINT R/W R/W
ReReRDY served served R R/W R/W
5. Sector Configuration
The table below shows the sector configuration of flash memory and lists the addresses of each sector for both during CPU access and a flash memory programming. * Sector configuration of flash memory Flash Memory 16 Kbytes 8 Kbytes 8 Kbytes
CPU Address FFFFH to C000H BFFFH to A000H 9FFFH to 8000H
Programmer Address* 1FFFFH to 1C000H 1BFFFH to 1A000H 19FFFH to 18000H
* : Programmer address The programmer address is the address to be used instead of the CPU address when programming data from a parallel flash memory programmer. Use the programmer address on programming or erasing using a generalpurpose parallel programmer. 13
MB89051 Series
6. ROM Programmer Adaptor and Recommended ROM Programmers
Package FPT-64P-M09 * Inquiry: Sunhayato Corp. Compatible adapter Sunhayato Corp. FLASH-64QF2-32DP-8LF3 Compatible programmers and models Ando Denki K.K. AF9708 (ver 1.60 or higher) AF9709 (ver 1.60 or higher)
Ando Denki K. K.
: TEL FAX E-mail : TEL
: 81-3-3984-7791 : 81-3-3971-0535 : adapter@sunhayato.co.jp : 81-3-3733-1160
14
MB89051 Series
s BLOCK DIAGRAM
X0 X1
Main clock oscillator
Clock control circuit
Reset output
Power on reset circuit (watchdog timer)
RST
PLL circuit
RPVP USB DRV RPVM D2VP D5VP D2VM D5VM
Rp Dp2-5
21-bit timebase timer USB HUB Circuit
Dp1
Nch I/O Port
Internal Bus
8 bit PWM timer
P46/UI/PWM1 P47/PWM2
CMOS I/O Port
CMOS I/O Port
P40/POW5 P41/POW2 P42/POW3 P43/POW4
USB Function Circuit
UART SIO
P44/UCK P45/UO
P00 P07, P10 P17
CMOS out Port
3 V CLK Port
CLK1
DMAC
P20 P27*
CLK2 P31/INT1 P32/INT2/SI1 P33/INT3/SO1 P34/INT4/SCK1 P35/INT5/SCK2 P36/INT6/SO2 P37/INT7/SI2
Clock output
External interrupt (level)
SIO1 SIO2 RAM 2 KByte F2MC - 8L CPU
3 V CMOS I/O Port Nch I/O Port
ROM 32 K / FLASH 32 KByte I2C
P53/SDA, P54/SCL
Other pins
VSS VCC MOD0 MOD1 MOD2 USBP C
* : Port 2 serves as an output-only terminal on the emulator.
15
MB89051 Series
s CPU CORE
1. Memory Size
The MB89051 microcontroller offers a memory space of 64 Kbytes consisting of the I/O, RAM and ROM areas. The memory space contains areas that are used for specific purposes, such as a general-purpose register and a vector table. * I/O area (addresses: 0000H through 007FH) This area is assigned with the control and data registers, for example, of peripheral functions to be built in. The I/O area is as accessible as the memory since the area is assigned to a part of the memory space.Direct addressing also allows the area to be accessed faster. * RAM area As an internal data area, a static RAM is built in. The internal RAM capacity varies with the product type. The area 80H to FFH can be accessed at high speed with direct addressing. The area 100H to 1FFH can be used a general-purpose register area. (The usable area is limited depending on the product.) When reset, RAM data becomes undefined. * ROM area As an internal program area, a ROM is built in. The internal RAM capacity varies with the product type. The area FFC0H to FFFFH should be used for a vector table, for example. * Memory map
MB89051 0000H I/O 0080H RAM 0100H
Register
MB89F051 0000H I/O 0080H RAM 0100H
Register
0200H
0200H
0880H
0880H
Access prohibited
8000H ROM FFC0H FFFFH FFC0H FFFFH 8000H
Access prohibited
ROM
Vector table (reset, interrupt and vector call instructions)
* : FLASH ROM
16
MB89051 Series
2. Registers
The MB89051 series has two types of registers; the registers dedicated to specific purposes in the CPU and the general-purpose registers. The dedicated registers are as follows: Program counter (PC) Accumulator (A) Temporary accumulator (T) Index register (IX) Extra pointer (EP) Stack pointer (SP) Program status (PS) 16 bits
PC A T IX EP SP RP PS CCR
: A 16-bit register to indicate locations where instructions are stored. A 16-bit register for temporary storage of operations. In the case of an 8-bit : data processing instruction, the lower one byte is used. A 16-bit register which performs operations with the accumulator.In the case of : an 8-bit data processing instruction, the lower one byte is used. : A 16-bit register for index modification. : A 16-bit register to point to a memory address. : A 16-bit register to indicate a stack area. : A 16-bit register to store a register pointer or a condition code.
: Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status
Initial value FFFDH Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate I-flag = 0, IL1, 0 = 11 Initial values for other bits are indeterminate.
The PS register can further be divided into the register bank pointer in the higher 8 bits (RP) and the condition code register in the lower 8 bits (CCR). (See the diagram below.)
RP bit15 bit14 bit13 bit12 bit11 bit10 bit9 R4 R3 R2 R1 R0 - - bit8 - bit7 H bit6 I bit5 IL1 CCR bit4 IL0 bit3 N bit2 Z bit1 V bit0 C
CCR initial value
X011XXXXB
PS
H-flag I-flag IL 1,0 N-flag Z-flag V-flag C-flag X: Undefined 17
MB89051 Series
The RP points to the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule shown next. Rule for Conversion of Actual Addresses in the General-purpose Register Area
RP higher bits
"0" "0" "0" "0" "0" "0" "0" "1" A8 R4 A7 R3 A6 R2 A5 R1 A4 R0 A3
OP code lower bits
b2 A2 b1 A1 b0 A0
Generated address A15 A14 A13 A12 A11 A10 A9
The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that control CPU operations at the time of an interrupt. H flag : The flag is set to "1" when an arithmetic operation results in a carry from bit 3 to bit 4 or in a borrow from bit 4 to bit 3. The bit is cleared to "0" in other instances.The flag is for decimal adjustment instructions; do not use for other than additions and subtractions. : Interrupt is enabled when this flag is set to "1." Interrupt is disabled when this flag is set to "0." The flag is set to "0" when reset. Indicates the level of the interrupt currently enabled.An interrupt is processed only if its level is : higher than the value this bit indicates. IL0 0 1 0 1 Interrupt level 1 2 3 Lower = no interruption High-low Higher
I flag IL1, 0
IL1 0 0 1 1 N flag Z flag V flag C flag
: The flag is set to "1" when an arithmetic operation results in setting of the MSB to "1" or is cleared to "0" when the MSB is set to "1." : The flag is set to "1" when an arithmetic operation results in "0" or is set to "0" in other instances. : The flag is set to "1" when an arithmetic operation results in two's complement overflow or is cleared to "0" if no overflow occurs. : The flag is set to "1" when an arithmetic operation results in a carry from bit 7 or in a borrow to bit 7. The flag is cleared to "0" if neither of them occurs. In the case of a shift instruction, the flag is set to the shift-out value.
18
MB89051 Series
The following general-purpose registers are provided: *General-purpose registers : 8-bit data storage registers
The general-purpose registers are 8 bits in length and located in the register banks in the memory.One bank contains eight registers and the MB89051 microcontrollers allow a total of 16 banks to be used at maximum. The bank currently in use is indicated by the register bank pointer (RP). Register Bank Configuration This address = 0100H + 8 x (RP)
R0 R1 R2 R3 R4 R5 R6 R7
16 banks
Memory area
19
MB89051 Series
s I/O MAP
Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H to 15H 16H to 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH CTR1 CTR2 CTR3 CMR1 CMR2 CKR SCS PWM control register 1 PWM control register 2 PWM control register 3 PWM compare register 1 PWM compare register 2 Clock output control register Serial clock switching register PURR0 PURR1 PURR2 PURR3 PURR4 PDR4 DDR4 PDR5 Port 4 data register Port 4 direction register Port 5 data register Reserved area Vacancy Port 0 pullup option setting register Port 1 pullup option setting register Port 2 pullup option setting register Port 3 pullup option setting register Port 4 pullup option setting register Reserved area R/W R/W R/W W W R/W R/W 00000000 000X0000 X 0 0 0 XXXX XXXXXXXX XXXXXXXX XXXXXXX 0 0 XXXXXXX 0 R/W R/W R/W R/W R/W 11111111 11111111 11111111 1111111X 11111111 PDR3/USBP DDR3/USBPC DDR2 SYCC STBC WDTC TBTC Port 2 direction register System clock control register Standby control register Watchdog timer control register Timebase timer control register Vacancy Port 3 data register/Pull-up register for USB Port 3 data direction register/ Pull-up control register for USB Reserved area Vacancy R/W R/W R/W XXXXXXXX 00000000 XXX 1 1 XXX R/W R/W XXXXXXXX 00000000 Register name PDR0 DDR0 PDR1 DDR1 PDR2 Register description Port 0 data register Port 0 direction register Port 1 data register Port 1 direction register Port 2 data register Reserved area R/W R/W R/W R/W R/W 00000000 XXX 1 1 X 0 0 0 0 0 1 XXXX XXXXXXXX 0 0 XXX 0 0 0 Read/write R/W W R/W W R/W Initial value XXXXXXXX 00000000 XXXXXXXX 00000000 00000000
(Continued)
20
MB89051 Series
Address 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH, 3FH 40H 41H 42H 43H 44H 45H 46H 47H 48H, 49H 4AH 4BH 4CH, 4DH 4EH 4FH 50H 51H 52H 53H 54H 55H
Register name FMCS SMC1 SMC2 SSD SIDR/SODR SRC IBSR IBCR ICCR IADR IDAR SMR1 SDR1 EIE EIF HMDR HDSR1 HDSR2 HDSR3 HSTR OCCR DADR
Register description Flash memory control status register (Only built-in Flash Memory products) Serial mode control register 1 Serial mode control register 2 Serial status and control register Serial input/serial output data register Serial rate control register I C bus status register I C bus control register I C clock regeister I C address register I C data register Vacancy Serial mode register 1 Serial data register 1 External interrupt control register External interrupt flag register Vacancy HUB mode register Hub descriptor register 1 Hub descriptor register 2 Hub descriptor register 3 Hub status register Over current register Descriptor ROM address register Reserved area Vacancy
2 2 2 2 2
Read/write R, R/W R/W R/W R R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 000X00X0 00000000 00000000 0 0 0 0 1 XXX XXXXXXXX XXXXXXXX 00000000 00011000 0 X 0 XXXXX XXXXXXXX XXXXXXXX 00000000 XXXXXXXX 00000000 XXXXXXX 0 1 0 XXXXX 0 XXXXXXXX XXXXXXXX XXXXXXXX 00000000 0 XXX 0 0 0 0 XXXXXXXX
SMR2 SDR2 HDSR4 UMDR DBAR TDCR0 TDCR1 TDCR21
Serial mode register 2 Serial data register 2 Vacancy Hub descriptor register 4 Vacancy USB reset mode register DMA base address register Transfer data count register 0 Transfer data count register 1 Reserved area Transfer data count register 2
R/W R/W R/W R/W R/W R/W R/W R/W
00000000 XXXXXXXX 0 0 0 0 0 1 01 1 0 0 0 XX 0 0 XXXXXXXX X0000000 X0000000 X0000000
(Continued)
21
MB89051 Series
(Continued)
Address 56H 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH 60H 61H 62H 63H 64H 65H 66H 67H to 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH ILR1 ILR2 ILR3 ILR4 TDCR3 UCTR USTR1 USTR2 UMSKR UFRMR1 UFRMR2 EPER EPBR0 EPBR11 EPBR12 EPBR21 EPBR22 EPBR31 EPBR32 USB control register USB status register 1 USB status register 2 USB interrupt mask register USB frame status register 1 USB frame status register 2 USB endpoint enable register End point setup register 0 Endpoint setup register 11 Endpoint setup register 12 Endpoint setup register 21 Endpoint setup register 22 Endpoint setup register 31 Endpoint setup register 32 Reserved area Vacancy Reserved area Vacancy Interrupt level setting register 1 Interrupt level setting register 2 level setting register 3 Interrupt level setting register 4 Reserved area W W W W 11111111 11111111 11111111 11111111 Register name Register description Reserved area Transfer data count register 3 R/W R/W R/W R R/W R R R/W R/W R/W R/W R/W R/W R/W R/W X0000000 00000000 00000000 XXXXXX 0 0 00000000 XXXXXXXX XXXXXXXX XXXX 0 0 0 1 X0000000 XX 0 0 0 0 XX X0000000 XX 0 0 0 0 XX X0000000 XX 0 0 0 0 XX X0000000 Read/write Initial value
* Information about read/write R/W: Read/write enabled, R: Read only, W: Write only * Information about initial values 0: The initial value of this bit is "0". 1: The initial bit of this bit is "1". X: The initial value of this bit is undefined. Note : Vacancies and reserved spaces are not for use.
22
MB89051 Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating Min VSS-0.3 VSS-0.3 Input voltage VI VSS-0.3 VSS-0.3 VSS-0.3 Output voltage VO VSS-0.3 VSS-0.3 Maximum clamp current Total maximum clamp cuurent "L" level maximum output current "L" level average output current "L" level total maximum output current "L" level total average output current "H" level maximum outputcurrent "H" level average outputcurrent "H" level total maximum output current "H" level maximum outputcurrent IOH ICLAMP |ICLAMP| IOL IOLAV IOL IOLAV IOH IOHAV -2.0 "H" level average total output currnt Power consumption Operating temperature Storage temperature IOHAV PD TA Tstg -40 -55 3.6 VSS+6.0 2.0 20 15 4 100 40 -15 -4 -50 -10 -20 -10 300 +85 +150 V V mA mA mA mA mA mA mA mA mA mA mA mA mW C C Max VSS+6.0 VCC+0.3 3.3 VSS+6.0 VCC+0.3 (VSS = 0 V) Symbol VCC Unit V V V V V Other than P31 to P37, P46, P47, P53, P54*1 P31 to P37 P46,P47,P53, P54*1 Other than P31 to P37, P46, P47, P53, P54, CLK1, CLK2, USBP P31 to P37, CLK1, CLK2, USBP P46, P47, P53, 54 *5 *5 Normal output*2 Normal output*3 Total normal output Total normal output*4 Normal output*2 Normal output*3 Total normal output Total output of P31 to P37, CLK1, CLK2, USBP. Total normal output*4 Total output of P31 to P37, CLK1, CLK2 and USBP.*4 Remarks
Parameter Power supply voltage
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. *1 : VI should not exceed the specified ratings. However, if the maximum current to /from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. *2 : Maximum output current is defined as the peak value at one curresponding pin. *3 : Average output current is defined as the average current flowing through one corresponding pin in an internal of 100 ms. (Average value : operating current x operating duty)
23
MB89051 Series
*4 : Average total output current is defined as the average current flowing through all corresponding pins in an internal of 100 ms. *5 : * Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P40 to P45 * Use within recommended operating conditions. * Use at DC voltage (current) * The +B signal should always be applied with a limiting resistance placed between the +B signal and the microcontroller. * The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instaneously or for prolonged periods. * Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potentional may pass through the protective diode and increase the potentional at the VCC pin, and this may affect other devices. * Note that if a +B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. * Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on result. * Care must be taken not to leave the +B input pin open. * Note that analog system input pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept +B signl input. * Sample recommended circuits : * Input/Output Equivalent circuits
Protective diode
VCC
Limiting resistance +B input (0 V to 16 V)
P-ch
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
24
MB89051 Series
2. Recommended Operating Conditions
Value Min 4.5 3.0 -40 Operating temperature TA 0 Smoothing capacitor Series resistance CS RS 0.1 16 +70 1.0 C F Typ Max 5.5 3.6 +85
(VSS = 0 V) Unit V V C Remarks At VCC = 5.0 V At VCC = 3.3 V* When the USB function is not in use. When the USB function is in use At VCC = 5.0 V* When the USB function is in use
Parameter Power supply voltage
Symbol VCC
*: Use either a ceramic capacitor or a capacitor with similar frequency characteristics.The capacity of the smoothing capacitor for the Vcc pin should be greater than that of the Cs.When using with a supply voltage of 3.3 V, connect pin C with Vcc to input 3.3 V. * C and USB Port Connection Diagram
RS D2VP RS D2VM RS RS RPVP RS RPVM D4VP C CS D4VM RS D5VP RS D5VM RS D3VM RS D3VP RS
25
MB89051 Series
* Operating voltage vs. Operating frequency
5.5 5.0 4.5 Guaranteed operation range
(V)
4.0
Operating voltage VCC
3.6 Guaranteed operation range 3.0
2.0
1.0
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0
CPU operating frequency (FCH MHz) (At instruction cycle 4/ FCH)
4.0
2.0
0.8
0.4
0.33
Minimum execution time (instruction cycle) (s) However, FCH = clock frequency (Fc) x 2
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
26
MB89051 Series
3. DC Characteristics (Power supply votage : 5.0 V)
Sym bol
(VCC = 5.0 V, VSS = 0 V, TA = -40 C to +85 C) Value Typ Max Unit Remarks
Parameter
Pin P00 to P07, P10 to P17, P20 to P27, P40 to P47, P53, P54, MOD0, MOD1, MOD2 P31 to P37 RST, UCK, UI
Condition
Min
VIH
0.7 VCC
VCC+0.3
V
"H" level Input voltage

2.5 0.8 VCC

3.3 VCC+0.3
V V
3V
VIHS INT1 to INT7, SCK1, SCK2, SI1, SI2 VIHI2C SCL, SDA P00 to P07, P10 to P17, P20 to P27, P40 to P47, P53, P54, MOD0, MOD1, MOD2 P31 to P37 RST, INT1 to INT7, UCK, UI INT1 to INT7, SCK1, SCK2, SI1, SI2
2.9 0.8 VCC
3.3 VCC+5.5
V V
3V
VIL
VSS-0.3
0.3 VCC
V
"L" level Input voltage

VSS-0.3 VSS-0.3

0.9 0.2 VCC V
3V
VILS

VSS-0.3 VSS-0.3 VSS-0.3

0.6 0.3 VCC VCC+0.3 V V
3V
VILI2C SCL, SDA Open-drain output application voltage VD1 P53, P54 P00 to P07, P10 to P17, P20 to P24, P40 to P47 P31 to P37, CLK1, CLK2 USBP
IOH = -2.0 mA
4.0
V
"H" level Output voltage
VOH
IOH = -1.0 mA IOH = -2.4 mA
2.6 3.0

3.6 V 3.6 V
V V
3V USB Pull up
(Continued)
27
MB89051 Series
(Continued)
Sym bol (VCC = 5.0 V, VSS = 0 V, TA = -40 C to + 85 C) Pin P00 to P07, P10 to P17, P20 to P24, P40 to P47, P53, P54, RST Condition Value Min Typ Max Unit Remarks
Parameter
"L" level Output voltage
IOL = 4.0 mA
0.4
V
VOL
P31 to P37, IOL = 1.0 mA CLK1, CLK2 P00 to P07, P10 to P17, P20 to P27, P31 to P37, P40 to P47, CLK1, CLK2 USBP Open-drain output leakage current ILIOD P53, P54 P00 to P07, P10 to P17, P20 to P27, RPULL P31 to P37, P40 to P47, P53, P54, RST ICC Power supply current VCC ICCS1 ICCH Input capacitance CIN 0.0 V < VI < VSS + 5.5 V
0.4
V
3V
Input leakage current (Hi-Z output leakage current)
-5 0.0 V < VI < VCC -5 -5
+5
A
ILI
When no pullup re sistance is speci fied

+5 +5 +5
A A A
Pullup resistance
VI = 0.0 V
25
50
100
k
RST is excluded when pullup resistance available is specified. MB89F051 MB89051 Sleep mode Stop
FCH = 12.0 MHz, VCC = 5.0 V, tinst = 0.333 s FCH = 12.0 MHz, VCC = 5.0 V, tinst = 0.333 s TA = + 25 C Other than VCC, VSS and f = 1 MHz C

29 28 20 40 5
42 41 30 70 15
mA mA mA A pF
28
MB89051 Series
4. DC Characteristics (Power supply votage : 3.3 V)
Sym bol
(VCC = 3.3 V, VSS = 0 V, TA = -40 C to +85 C) Value Typ Max Unit Remarks
Parameter
Pin P00 to P07, P10 to P17, P20 to P27, P31 to P37, P40 to P47, P53, P54, MOD0, MOD1, MOD2
Condition
Min
VIH
0.7 VCC
VCC+0.3
V
"H" level Input voltage
RST, UCK, UI, VIHS INT1 to INT7, SCK1, SCK2, SI1, SI2 VIHI2C SCL, SDA P00 to P07, P10 to P17, P20 to P27, P31 to P37, P40 to P47, P53, P54, MOD0, MOD1, MOD2
0.8 VCC
VCC+0.3
V
0.8 VCC
VCC+5.5
V
VIL
VSS-0.3
0.3 VCC
V
"L" level Input voltage
RST, INT1 to INT7, UCK, UI, VILS INT1 to INT7, SCK1, SCK2, SI1, SI2 VILI2C SCL, SDA
VSS-0.3
0.2 VCC
V

VSS-0.3 VSS-0.3

0.3 VCC VCC+0.3
V V
Open-drain output application voltage
VD1
P53, P54 P00 to P07, P10 to P17, P20 to P24, P40 to P47
IOH = -2.0 mA
2.6
V
"H" level Output voltage
VOH P31 to P37, CLK1, CLK2 USBP
IOH = -1.0 mA IOH = -2.4 mA
2.6

V USB Pull up, Vcc = 3.1 V to 3.6 V
3.0
V
(Continued)
29
MB89051 Series
(Continued)
Sym bol (VCC = 3.3 V, VSS = 0 V, TA = -40 C to +85 C) Pin Condition Value Min Typ Max Unit Remarks
Parameter
"L" level Output voltage
P00 to P07, P10 to P17, P20 to P24, P40 to P47, VOL P53, P54, RST
IOL = 4.0 mA
0.4
V
P31 to P37, IOL = 1.0 mA CLK1, CLK2 P00 to P07, P10 to P17, P20 to P27, P31 to P37, P40 to P47, CLK1, CLK2 USBP Open-drain output leakage current ILIOD P53, P54 P00 to P07, P10 to P17, P20 to P27, RPULL P31 to P37, P40 to P47, P53, P54, RST ICC Power supply current VCC ICCS1 ICCH Input capacitance CIN 0.0 V < VI < VSS+5.5 V
0.4
V
Input leakage current (Hi-Z output leakage current)
-5 0.0 V < VI < VCC -5 -5
+5
A
ILI
When no pullup resistance is specified

+5 +5 +5
A A A
Pullup resistance
VI = 0.0 V
25
50
100
k
RST is excluded when pullup resistance available is specified.
FCH = 12.0 MHz, VCC = 3.3 V, tinst = 0.333 s FCH = 12.0 MHz, VCC = 3.3 V, tinst = 0.333 s TA = +25 C Other than f = 1 MHz Vcc and Vss

29 28 20 40 10
42 41 30 70
mA MB89F051 mA MB89051 mA Sleep mode A pF Stop
30
MB89051 Series
5. AC Characteristics
(1) Reset Timing (VCC = 5.0 V, VSS = 0 V, TA = -40 C to +85 C) Symbol tZLZH Condition Value Min 48 tHCYL Max Unit ns Remarks
Parameter RST "L" pulse width
Notes : * tHCYL is the oscillation cycle for the internal main clock. * If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the external reset pin (RST).
tZLZH
RST
0.2 VCC
0.2 VCC
(2) Power-on reset Value Min 0.066 4 Max 50
(VSS = 0 V, TA = -40 C to +85 C) Symbol tR tOFF Condition Unit ms ns Due to repeated operations Remarks
Parameter Power supply rising time Power supply cutoff time
Note : The power supply must be up within the selected oscillation stabilization time. When the supply voltage needs to be varied while operating, it is recommended to smoothly start up the voltage.
tR 3.5 V
tOFF
VCC
0.2 V 0.2 V 0.2 V
31
MB89051 Series
(3) Clock Timing Value Min Typ 6 166.6 12 83.3 Max
(VSS = 0 V, TA = -40 C to +85 C) Symbol Pin name Condition FC tXCYL FCH tHCYL X0, X1 X0, X1 Unit MHz ns MHz ns Twice the Fc tXCYL/2 Remarks
Parameter Clock frequency Clock cycle time Internal main clock frequency Internal clock cycle
* X0 and X1 Timing and Conditions
tXCYL
X0
0.2 VCC 0.2 VCC
* Clock Conditions When a crystal resonator is used
X0
X1
C1
C2
(4) Instruction Cycle Parameter Instruction cycle (Min execution time) Symbol tinst Value 4 / FCH, 8 / FCH, 16 / FCH, 64 / FCH Unit s
(VSS = 0 V, TA = -40 C to +85 C) Remarks When operating at FCH = 12 MHz tinst = 0.33 s (4 / FCH)
32
MB89051 Series
(5) UART Serial I/O Timing
(VCC = 5.0 V, VSS = 0 V, TA = -40 C to +85 C) Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name UCK UCK, UO UI, UCK UCK, UI UCK UCK, UO UI, UCK UCK, UI External shift clock mode Internal shift clock mode Condition Value Min 2 tinst* -200 200 200 1 tinst* 1 tinst* 0 200 200 Max +200 200 Unit s ns ns ns s s ns ns ns Remarks
Parameter Serial clock cycle time UCK UO Valid UI UCK UCK valid UI hold time Serial clock "H" pulse width Serial clock "L" pulse width UCK UO time Valid UI UCK UCK valid UI hold time
* : For information on tinst, see " (4) Instruction Cycle". * Internal shift clock mode
tSCYC
UCK
0.2 Vcc tSLOV 0.8 Vcc 0.2 Vcc tIVSH
0.8 Vcc 0.2 Vcc
UO
tSHIX 0.8 VCC 0.2 VCC
UI
0.8 VCC 0.2 VCC
* External shift clock mode
tSLSH tSHSL 0.8 VCC 0.2 VCC tSLOV 0.8 Vcc 0.2 Vcc tIVSH tSHIX 0.8 VCC 0.2 VCC 0.2 VCC 0.8 VCC
UCK
UO
UI
0.8 VCC 0.2 VCC
33
MB89051 Series
(6) Serial I/O Timing
(VCC = 5.0 V, Vss = 0V, TA = -40 C to +85 C) Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name SCK1, SCK2 SCK1, SO1, SCK2, SO2 SCK1, SI1, SCK2, SI2 SCK1, SI1, SCK2, SI2 SCK1, SCK2 SCK1, SCK2 SCK1, SO1, SCK2, SO2 SCK1, SI1, SCK2, SI2 SCK1, SI1, SCK2, SI2 External shift clock mode Internal shift clock mode Condition Value Min 2 tinst* -200 200 200 tinst* tinst* 0 200 200 Max +200 200 Unit s ns ns ns s s ns s s Remarks
Parameter Serial clock cycle time SCK SO time Valid SI SCK SCK Valid SI hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SO time Valid SI SCK SCK Valid SI hold time
* : For information on tinst, see " (4) Instruction Cycle". * Internal shift clock mode
tSCYC 2.9
SCK1 SCK2
0.6 tSLOV
0.6
SO1 SO2
2.9 0.6 tIVSH tSHIX 2.9 0.6
SI1 SI2
2.9 0.6
* External shift clock mode
tSLSH 2.9 tSHSL 2.9
SCK1 SCK2
0.6
0.6 tSLOV
SO1 SO2
2.9 0.6 tIVSH tSHIX 2.9 0.6
SI1 SI2
2.9 0.6
34
MB89051 Series
(7) Peripheral Input Timing
(VCC = 5.0 V, VSS = 0 V, TA = -40 C to +85 C) Pin name Condition INT1 to INT7 tIHIL1 2 tinst* s Value Min 2 tinst* Max Unit s Remarks
Parameter Peripheral input "H" pulse width 1 Peripheral input "L" pulse width 1
Symbol tILIH1
* : For information on tinst, see " (4) Instruction Cycle".
tIHIL1
tILIH1 2.9 0.8 VCC
INT1 ~ INT7
0.6
0.6
35
MB89051 Series
(8) I2C Timing Parameter Start condition output Stop condition output Start condition detect Stop condition detect Sym bol tSTA tSTO tSTA tSTO Pin SCL, SDA SCL, SDA SCL, SDA SCL, SDA SCL, SDA SCL, SDA SCL SCL SDA (VCC = 5.0 V, VSS = 0 V, TA = -40 C to +85 C) Value Min 1 / 4 x tinst*1 x mt* x nt*3 - 20 1 / 4 x tinst*1 x (mt*2 x nt*3 + 8) - 20 1 / 4 x tinst*1 x 6 + 40 1 / 4 x tinst*1 x 6 + 40 1 / 4 x tinst*1 x (mt*2 x nt*3 + 8) - 20 1 / 4 x tinst*1 x 4 + 40 1 / 4 x tinst*1 x mt*2 x nt*3 - 20 1 / 4 x tinst*1 x (mt*2 x nt*3 + 8) - 20 1 / 4 x tinst*1 x 4 - 20 1 / 4 x tinst*1 x 4 - 20 1 / 4 x tinst*1 x 6 + 40 1 / 4 x tinst*1 x 2 + 40 40 0 Max 1 / 4 x tinst*1 x mt*2 x nt*3 + 20 1 / 4 x tinst*1 x (mt*2 x nt*3 + 8) + 20 1 / 4 x tinst*1 x (mt*2 x nt*3 + 8) + 20 1 / 4 x tinst*1 x mt*2 x nt*3 + 20 1 / 4 x tinst*1 x (mt*2 x nt*3 + 8) + 20 1 / 4 x tinst*1 x 4 + 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Master mode Master mode Master mode Remarks Master mode Master mode
Restart condition output tSTASU Restart condition detect tSTASU SCL output Low width SCL output High width SDA output delay SDA output setup time after interrupt SCL input Low pulse width SCL input High pulse width SDA input setup time SDA hold time tLOW tHIGH tDO
tDOSU SDA tLOW tHIGH tSU tHO SCL SCL SDA SDA
*1 : For information on tinst, see " (4) Instruction Cycle". *2 : m is defined in the ICCR CS 4 to CS 3 (bit 4 to bit 3) . *3 : n is defined in the ICCR CS 2 to CS 0 (bit 2 to bit 0) . Data transmit (master/slave)
tDO SDA tSTASU tSTA SCL tLOW tHO 1 9 tDO tSU tSU ACK tDOSU
Data receive (master/slave)
tSU SDA tHIGH SCL 6 7 tLOW 8 9 tHO tDO ACK tSTO tDO tDOSU
36
MB89051 Series
6. FLASH Program/Erase characteristics
* Program/Erase characteristics Parameter Sector erase time Chip erase time Byte program time Prgram/erase cycle TA = +25 C Vcc = 5.0 V Condition Value Min 10,000 Typ 1 5 8 Max 15 75 3,600 Unit s s s cycle Remarks Except for the write time before internal erase operation Except for the write time before internal erase operation Except for the over head time of the system.
37
MB89051 Series
s ORDERING INFORMATION
Part Number MB89051PFM MB89F051PFM Package 64-pin plastic LQFP (FPT-64P-M09) Remarks
38
MB89051 Series
s PACKAGE DIMENSIONS
64-pin plastic LQFP (FPT-64P-M09) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
14.000.20(.551.008)SQ
* 12.000.10(.472.004)SQ
48 33
0.1450.055 (.0057.0022)
49
32
0.10(.004) Details of "A" part 1.50 -0.10 .059 -.004
+0.20 +.008
(Mounting height)
0.25(.010) INDEX 0~8
64 17
1
16
"A"
0.65(.026)
0.320.05 (.013.002)
0.500.20 (.020.008) 0.600.15 (.024.006)
0.100.10 (.004.004) (Stand off)
0.13(.005)
M
C
2003 FUJITSU LIMITED F64018S-c-3-5
Dimensions in mm (inches) Note : The values in parentheses are reference values.
39
MB89051 Series
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0303 (c) FUJITSU LIMITED Printed in Japan

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